Many electronic devices employ microprocessors or other digital circuits that require one or more clock signals for synchronization and other functions. A clock signal permits precise timing of events in the microprocessor, for example. Typical microprocessors may be supervised or synchronized by a free-running oscillator, such as an oscillator driven by a crystal, an LC-tuned circuit or an external clock source. Clocking rates up to 40 MHz, 66 MHz, 100 MHz, 133 MHz, 200 MHz and beyond are common in personal computers. The parameters of a clock signal are typically specified for a microprocessor and may include minimum and maximum allowable clock frequencies, tolerances on the high and low voltage levels, maximum rise and fall times on the waveform edges, pulse-width tolerance if the waveform is not a square wave and the timing relationship between clock phase if two-clock phase signals are needed.
High performance microprocessor-based devices using leading edge, high-speed circuits are particularly susceptible to generating and radiating electromagnetic interference (EMI). The spectral components of the EMI emissions typically have peak amplitudes at harmonics (i.e., whole number multiples) of the fundamental frequency of the clock circuit. Accordingly, many regulatory agencies, such as the FCC in the United States, have established testing procedures and maximum allowable emissions for such products.
Practical synchronous digital systems radiate electromagnetic energy in a number of narrow bands at the clock frequency and its harmonics, resulting in a frequency spectrum that, at certain frequencies, can exceed regulatory limits for electromagnetic interference. In order to comply with government limits on EMI emissions, costly suppression measures or extensive shielding may be required. Other approaches for reducing EMI include careful routing of signal traces on printed circuit boards to minimize loops and other potentially radiating structures. Unfortunately, such an approach often leads to more expensive multilayer circuit boards with internal ground planes. In addition, greater engineering effort must go into reducing EMI emissions. The difficulties caused by EMI emissions are made worse at higher processor and clock speeds.
An alternative approach is to reduce the spectral density of the EMI by lowering the peak energy emissions at harmonics using a spread spectrum clock signal. This approach consists of modulating the frequency of the clock signal by either a regular function such as a triangular wave or by a pseudo-random function. This method distributes the energy of the clock signal over a wider frequency range, thereby reducing its peak spectral density. This procedure works because the EMI receivers used by testing laboratories divide the electromagnetic spectrum into frequency bands approximately 120 kHz wide. If the system under test were to radiate all of its energy at one frequency, then this energy would fall into a single frequency band of the receiver, which would register a large peak at that frequency. Spread spectrum clocking distributes the energy so that it falls into a large number of the receiver's frequency bands, without putting enough energy into any one band to exceed the statutory limits.
FIG. 1 is a schematic illustration of this effect where the spectral amplitude versus frequency at a harmonic (NF) is indicated by the plot labeled M. As also shown, the spectrum at the harmonic of a standard clock signal is given as an impulse function labeled I. The spectrum of the spread spectrum clock signal at the same harmonic frequency ideally assumes a trapezoidal shape as illustrated by the plot labeled T.
FIG. 2 is a block diagram of a spread spectrum clock generator circuit 10 including a phase locked loop (PLL), such as proposed in U.S. Pat. Nos. 5,488,627, 5,631,920, 5,867,524 and 5,827,807, the entirety of which are hereby incorporated by reference herein. The PLL 10 includes a first frequency divider 12, a phase detector 14, low pass filter 16, voltage controlled oscillator 18 and second frequency divider 20. The circuit 10 frequency modulates an externally generated clock signal designated “Ref”, such as a signal generated by a piezoelectric crystal driven at its resonant frequency by a suitable driver or oscillator circuit, to provide a spread spectrum output clock signal CLK. The frequency modulation of the clock signal reduces spectral amplitude of the EMI components at each harmonic of the clock when compared to the spectrum of the same clock signal without modulation.
Although the spread spectrum clock signal circuit 10 can reduce the EMI emissions in an electronic device, the modulation is done through a complex PLL circuit as illustrated. Further, the output clock signal is mostly influenced by the phase noise of the oscillator circuit 18 but not the reference signal Ref. The reference signal passes through the VCO 18 and is fed back through the phase detector 14. If the reference signal is a very high frequency input and the phase noise of the VCO 18 is not proper with respect to the high frequency reference signal, the VCO 18 will influence the precision of the output clock signal.
Therefore, there remains a need for a less complex circuit and method for generating a spread spectrum clock signal. Still further, there remains a need for a circuit and method for generating a spread spectrum clock signal with improved phase noise.